VHDL Logical Operators and Signal Assignments for Combinational Logic

In this post, we discuss the VHDL logical operators, when-else statements , with-select statements and instantiation . These basic techniques allow us to model simple digital circuits.

In a previous post in this series, we looked at the way we use the VHDL entity, architecture and library keywords. These are important concepts which provide structure to our code and allow us to define the inputs and outputs of a component.

However, we can't do anything more than define inputs and outputs using this technique. In order to model digital circuits in VHDL, we need to take a closer look at the syntax of the language.

There are two main classes of digital circuit we can model in VHDL – combinational and sequential .

Combinational logic is the simplest of the two, consisting primarily of basic logic gates , such as ANDs, ORs and NOTs. When the circuit input changes, the output changes almost immediately (there is a small delay as signals propagate through the circuit).

Sequential circuits use a clock and require storage elements such as flip flops . As a result, changes in the output are synchronised to the circuit clock and are not immediate. We talk more specifically about modelling combinational logic in this post, whilst sequential logic is discussed in the next post.

Combinational Logic

The simplest elements to model in VHDL are the basic logic gates – AND, OR, NOR, NAND, NOT and XOR.

Each of these type of gates has a corresponding operator which implements their functionality. Collectively, these are known as logical operators in VHDL.

To demonstrate this concept, let us consider a simple two input AND gate such as that shown below.

The VHDL code shown below uses one of the logical operators to implement this basic circuit.

Although this code is simple, there are a couple of important concepts to consider. The first of these is the VHDL assignment operator (<=) which must be used for all signals. This is roughly equivalent to the = operator in most other programming languages.

In addition to signals, we can also define variables which we use inside of processes. In this case, we would have to use a different assignment operator (:=).

It is not important to understand variables in any detail to model combinational logic but we talk about them in the post on the VHDL process block .

The type of signal used is another important consideration. We talked about the most basic and common VHDL data types in a previous post.

As they represent some quantity or number, types such as real, time or integer are known as scalar types. We can't use the VHDL logical operators with these types and we most commonly use them with std_logic or std_logic_vectors.

Despite these considerations, this code example demonstrates how simple it is to model basic logic gates.

We can change the functionality of this circuit by replacing the AND operator with one of the other VHDL logical operators.

As an example, the VHDL code below models a three input XOR gate.

The NOT operator is slightly different to the other VHDL logical operators as it only has one input. The code snippet below shows the basic syntax for a NOT gate.

  • Mixing VHDL Logical Operators

Combinational logic circuits almost always feature more than one type of gate. As a result of this, VHDL allows us to mix logical operators in order to create models of more complex circuits.

To demonstrate this concept, let’s consider a circuit featuring an AND gate and an OR gate. The circuit diagram below shows this circuit.

The code below shows the implementation of this circuit using VHDL.

This code should be easy to understand as it makes use of the logical operators we have already talked about. However, it is important to use brackets when modelling circuits with multiple logic gates, as shown in the above example. Not only does this ensure that the design works as intended, it also makes the intention of the code easier to understand.

  • Reduction Functions

We can also use the logical operators on vector types in order to reduce them to a single bit. This is a useful feature as we can determine when all the bits in a vector are either 1 or 0.

We commonly do this for counters where we may want to know when the count reaches its maximum or minimum value.

The logical reduction functions were only introduced in VHDL-2008. Therefore, we can not use the logical operators to reduce vector types to a single bit when working with earlier standards.

The code snippet below shows the most common use cases for the VHDL reduction functions.

Mulitplexors in VHDL

In addition to logic gates, we often use multiplexors (mux for short) in combinational digital circuits. In VHDL, there are two different concurrent statements which we can use to model a mux.

The VHDL with select statement, also commonly referred to as selected signal assignment, is one of these constructs.

The other method we can use to concurrently model a mux is the VHDL when else statement.

In addition to this, we can also use a case statement to model a mux in VHDL . However, we talk about this in more detail in a later post as this method also requires us to have an understanding of the VHDL process block .

Let's look at the VHDL concurrent statements we can use to model a mux in more detail.

VHDL With Select Statement

When we use the with select statement in a VHDL design, we can assign different values to a signal based on the value of some other signal in our design.

The with select statement is probably the most intuitive way of modelling a mux in VHDL.

The code snippet below shows the basic syntax for the with select statement in VHDL.

When we use the VHDL with select statement, the <mux_out> field is assigned data based on the value of the <address> field.

When the <address> field is equal to <address1> then the <mux_out> signal is assigned to <a>, for example.

We use the the others clause at the end of the statement to capture instance when the address is a value other than those explicitly listed.

We can exclude the others clause if we explicitly list all of the possible input combinations.

  • With Select Mux Example

Let’s consider a simple four to one multiplexer to give a practical example of the with select statement. The output Q is set to one of the four inputs (A,B, C or D) depending on the value of the addr input signal.

The circuit diagram below shows this circuit.

This circuit is simple to implement using the VHDL with select statement, as shown in the code snippet below.

VHDL When Else Statements

We use the when statement in VHDL to assign different values to a signal based on boolean expressions .

In this case, we actually write a different expression for each of the values which could be assigned to a signal. When one of these conditions evaluates as true, the signal is assigned the value associated with this condition.

The code snippet below shows the basic syntax for the VHDL when else statement.

When we use the when else statement in VHDL, the boolean expression is written after the when keyword. If this condition evaluates as true, then the <mux_out> field is assigned to the value stated before the relevant when keyword.

For example, if the <address> field in the above example is equal to <address1> then the value of <a> is assigned to <mux_out>.

When this condition evaluates as false, the next condition in the sequence is evaluated.

We use the else keyword to separate the different conditions and assignments in our code.

The final else statement captures the instances when the address is a value other than those explicitly listed. We only use this if we haven't explicitly listed all possible combinations of the <address> field.

  • When Else Mux Example

Let’s consider the simple four to one multiplexer again in order to give a practical example of the when else statement in VHDL. The output Q is set to one of the four inputs (A,B, C or D) based on the value of the addr signal. This is exactly the same as the previous example we used for the with select statement.

The VHDL code shown below implements this circuit using the when else statement.

  • Comparison of Mux Modelling Techniques in VHDL

When we write VHDL code, the with select and when else statements perform the same function. In addition, we will get the same synthesis results from both statements in almost all cases.

In a purely technical sense, there is no major advantage to using one over the other. The choice of which one to use is often a purely stylistic choice.

When we use the with select statement, we can only use a single signal to determine which data will get assigned.

This is in contrast to the when else statements which can also include logical descriptors.

This means we can often write more succinct VHDL code by using the when else statement. This is especially true when we need to use a logic circuit to drive the address bits.

Let's consider the circuit shown below as an example.

To model this using a using a with select statement in VHDL, we would need to write code which specifically models the AND gate.

We must then include the output of this code in the with select statement which models the multiplexer.

The code snippet below shows this implementation.

Although this code would function as needed, using a when else statement would give us more succinct code. Whilst this will have no impact on the way the device works, it is good practice to write clear code. This help to make the design more maintainable for anyone who has to modify it in the future.

The VHDL code snippet below shows the same circuit implemented with a when else statement.

Instantiating Components in VHDL

Up until this point, we have shown how we can use the VHDL language to describe the behavior of circuits.

However, we can also connect a number of previously defined VHDL entity architecture pairs in order to build a more complex circuit.

This is similar to connecting electronic components in a physical circuit.

There are two methods we can use for this in VHDL – component instantiation and direct entity instantiation .

  • VHDL Component Instantiation

When using component instantiation in VHDL, we must define a component before it is used.

We can either do this before the main code, in the same way we would declare a signal, or in a separate package.

VHDL packages are similar to headers or libraries in other programming languages and we discuss these in a later post.

When writing VHDL, we declare a component using the syntax shown below. The component name and the ports must match the names in the original entity.

After declaring our component, we can instantiate it within an architecture using the syntax shown below. The <instance_name> must be unique for every instantiation within an architecture.

In VHDL, we use a port map to connect the ports of our component to signals in our architecture.

The signals which we use in our VHDL port map, such as <signal_name1> in the example above, must be declared before they can be used.

As VHDL is a strongly typed language, the signals we use in the port map must also match the type of the port they connect to.

When we write VHDL code, we may also wish to leave some ports unconnected.

For example, we may have a component which models the behaviour of a JK flip flop . However, we only need to use the inverted output in our design meaning. Therefore, we do not want to connect the non-inverted output to a signal in our architecture.

We can use the open keyword to indicate that we don't make a connection to one of the ports.

However, we can only use the open VHDL keyword for outputs.

If we attempt to leave inputs to our components open, our VHDL compiler will raise an error.

  • VHDL Direct Entity Instantiation

The second instantiation technique is known as direct entity instantiation.

Using this method we can directly connect the entity in a new design without declaring a component first.

The code snippet below shows how we use direct entity instantiation in VHDL.

As with the component instantiation technique, <instance_name> must be unique for each instantiation in an architecture.

There are two extra requirements for this type of instantiation. We must explicitly state the name of both the library and the architecture which we want to use. This is shown in the example above by the <library_name> and <architecture_name> labels.

Once the component is instantiated within a VHDL architecture, we use a port map to connect signals to the ports. We use the VHDL port map in the same way for both direct entity and component instantiation.

Which types can not be used with the VHDL logical operators?

Scalar types such as integer and real.

Write the code for a 4 input NAND gate

We can use two different types of statement to model multiplexors in VHDL, what are they?

The with select statement and the when else statement

Write the code for an 8 input multiplexor using both types of statement

Write the code to instantiate a two input AND component using both direct entity and component instantiation. Assume that the AND gate is compiled in the work library and the architecture is named rtl.

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Assignment Symbol in VHDL

VHDL assignments are used to assign values from one object to another. In VHDL there are two assignment symbols:

Either of these assignment statements can be said out loud as the word “gets”. So for example in the assignment: test <= input_1; You could say out loud, “The signal test gets (assigned the value from) input_1.”

Note that there is an additional symbol used for component instantiations (=>) this is separate from an assignment.

Also note that <= is also a relational operator (less than or equal to). This is syntax dependent. If <= is used in any conditional statement (if, when, until) then it is a relational operator , otherwise it’s an assignment.

One other note about signal initialization: Signal initialization is allowed in most FPGA fabrics using the := VHDL assignment operator. It is good practice to assign all signals in an FPGA to a known-value when the FPGA is initialized. You should avoid using a reset signal to initialize your FPGA , instead use the := signal assignment.

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Operators in VHDL – Easy explanation

In this post, we will take a look and understand the working of operators in VHDL. Operators are great tools that offer us room to maneuver in our program. The main purpose of any code is to implement some kind of logic. Having a variety of operators helps in that endeavor. The operators in VHDL are divided into four categories:

Arithmetic operators

Shift operators, relational operators, logical operators.

Each operator serves a well-defined purpose, and here we will learn to use these operators to our advantage in our programs. We’ll be using all of these operators extensively in our future modules in this VHDL course . Proper usage of operators can make a rather complex task shorter. Let’s first summarize all the operators in a neat little list that you can screenshot and keep handy.

Let’s dive into these operators.

For the sake of simplicity, let’s classify the operators into three categories.

Basic arithmetic operators

Advanced arithmetic operators, special arithmetic operators.

Basic arithmetic operators are used in almost every program, we will constantly come across examples, and they are easy to use with very low to no syntax restrictions.

Advanced arithmetic operators are not as frequently used but are equally important and powerful if used correctly. Again it is easy to use with a few syntax restrictions.

Special arithmetic operators perform nearly identical operations to simple arithmetic operators, the only difference being they are used under special conditions, with a specific syntax.

The four basic arithmetic operators include,

  • Subtraction -
  • Multiplication *

We can use these operators to perform basic mathematics in VHDL, and the syntax is as follows.

A simple addition operator, the syntax is as follows

A '+' sign is used to specify the addition between two numeric values. The <numeric> is any numeric value given for addition, the yield is a summation of both the numeric values.

Subtraction

A simple subtraction operator, the syntax is as follows

A '-' sign is used to specify the subtraction between two numeric values. The <numeric> is any numeric value given for subtraction, the yield is the difference for both the numeric values.

Multiplication

A multiplicative operator, the syntax is as follows

A '*' sign is used to specify the multiplication between two numeric values. The <numeric>  is any numeric value given for subtraction, the yield is the multiplication of both the numeric values.

A Division operator, the syntax is as follows

A '/' sign is used to specify the division between two numeric values. The <numeric> is any numeric value given for subtraction, and the yield is the quotient after the division of both the numeric values.

Moving on to advanced mathematical operators. Here we have the following operators:

  • Exponent  **
  • Absolute value  abs
  • Modulo  mod
  • Remainder  rem
  • Component not

These operators are extremely important for advanced mathematics in VHDL. Let us have a look at the syntax for these operators.

For the exponent operator, the syntax is as follows:

A '**' sign is used to specify the use of exponentiation. The <numeric> is any numeric value given for the operation, and the yield is the exponentiation of the numeric values. Let’s use an equation to understand the syntax better.

 { <numeric> }^{ <numeric> }

Absolute value

For the absolute value operator, the syntax is as follows:

An 'abs' is used to specify the absolute value. The <numeric> is any numeric value given for the operation, and the yield is the absolute value, a.k.a. modulus for the given numeric value.

A modulo operator, the syntax is as follows

A 'mod' is used to specify the modulo operator. <integer> values are used for the operation, and the yield is the modulo for the given integer values.

For the remainder operator, the syntax is as follows:

An 'rem' is used to specify the remainder operator. The <integer> values are used for the operation, and the yield is the remainder for the given integer values.

For the complement operator, the syntax is as follows:

A 'not' is used to specify the complement operator. Logic or boolean data type (TRUE or FALSE) is used for this operation, the result is of the same data type and is a complement of the data provided.

Special arithmetic operators are used when special conditions arise. These operators include,

  • Unary plus  +
  • Unary minus  -
  • Concatenation  &

For the unary plus operator, the syntax is as follows:

An '+' is used before the <numeric> to specify a unary plus operator. The <numeric> value is used for the operation, and the yield is a numeric value. When this operator is used, the numeric value returns unchanged.

Unary minus

An '-' is used before the <numeric> to specify a unary minus operator. The <numeric> value is used for the operation, and the yield is a numeric value. When this operator is used, the numeric value returns with the negated sign. Remember to use this operator with parenthesis in the case of any other operator preceding it. For example, 4 * -2 is invalid. It should be 4 * (-2).

Concatenation

For the concatenation operator, the syntax is as follows:

An '&' is used before the <array or element> to specify a concatenation operator. The <array or element> value is used for the operation, and the yield is a concatenation (joining) of the arrays or elements value.

Shift operators are used to shift an element of an array of numbers or alphabets left or right by a desired number of steps. Further elaboration with each operator is provided below. Shift operators include:

  • Shift Left logical  sll &  Shift Right logical srl
  • Shift Left arithmetic  sla   &  Shift Right arithmetic  sra
  • Rotate Left  rol   &  Rotate Right  ror

Shift Left logical  &  Shift Right logical

The sll is the left logical shifter and srl is the right logical shifter. The <integer> is used as the number of times we want to shift <logical array> left or right logically. The result of these operations is also a logical array.

Shift Left arithmetic  &  Shift Right arithmetic

The sla is the left arithmetic shifter and sra is the right arithmetic shifter. The <integer> is used as the number of times we want to shift <logical array> left or right arithmetically. The result of these operations is also a logical array.

Rotate Left and Rotate Right

The rol is the left rotator and ror is the right rotator. The <integer> is used as the number of times we want to rotate <logical array> left or right. The result of these operations is also a logical array.

Shift Functions 

A more optimum method for the implementation of shifting is by using shift functions. Shift functions are found in the numeric_std package of VHDL. These instructions have a simple syntax and are easy to understand. The keywords are shift_left() and shift_right() . The functions require two inputs: the signal to shift and the number of bits to shift by. There are two types of shifting:

  • Arithmetic shift – Here, the positions left vacant after shifting are substituted with the right bits to keep the sign of the original number intact.
  • Logical shift – Here, the positions left vacant after shifting are filled with ‘0’.

We can perform shifting logically and arithmetically use keywords unsigned and signed respectively.

Let us have a look at the syntax.

The <initial_string> could be any kind of string std_logic , signed , unsigned etc. The shift_left indicates a shift towards the left and shift_right indicated a shift towards the right. And the <integer> is used to indical the number of steps we want the string to be shifted.

As the name suggests, relational operators are used to test the quantitative relationship of two numbers or/and characters. It could also be two strings/arrays of numbers or characters.

We use these relational operators to compare these elements, and the result is a yield of boolean values: 1=true and 0=false.

The relational operators include

  • Test for equality =   and inequality  /=
  • Test for less than < and less than or equal <=
  • Test for greater than > and greater than or equal >=

Test for equality and inequality

These operators check if the given data is equal or not. In the case of the test for equality ‘=,’ if the given data is equal, the result is a boolean true, and if unequal, the result is a boolean false.

In the case of the test for inequality ‘/=,’ if data is inequal, the result is a boolean true, and if the data is equal, the result is a boolean false. Let us use an ‘if-else’ statement to better understand the concept.

The <instance_A>, <instance_B> are data instances of any data type. In the first process, the test for equality if <instance_A> is equal to <instance_B> only then the <instance_C> is given a binary 1 value. If <instance_A> and <instance_B> are not equal the <instance_C> is given a binary 0 value.

In the second process, the test for inequality if <instance_A> is not equal to <instance_B> only then the <instance_C> is given a binary 1 value. If <instance_A> and <instance_B> are equal the <instance_C> is given a binary 0 value.

Test for less than and less than or equal

These operators check the relation for the given data A and B. In the case of less than ‘<‘, if in the given data A is less than but not equal to B, the result is a boolean true. And if A is greater than or equal to B, the result is a boolean false.

In the case of test for less than or equal ‘<=’, if A is less than or equal to B, the result is a boolean true. And if A is greater than B, the result is a boolean false. Let us use an ‘if-else’ statement to better understand the concept.

The <instance_A>, <instance_B> are data instances of any data type. In the first process, the test for less than if <instance_A> is less then and not equal to <instance_B> only then the <instance_C> is given a binary 1 value. If <instance_A> greater than or equal to <instance_B> only then the <instance_C> is given a binary 0 value.

In the second process, the test for less than or equal if <instance_A> is less than or equal to <instance_B> only then the <instance_C> is given a binary 1 value. If <instance_A> greater <instance_B> only then the <instance_C> is given a binary 0 value.

Test for greater than and greater than or equal

These operators check the relationship between given data A and B. In the case of greater than ‘>’, if A is greater than but not equal to B, the result is a boolean true. If A is less than or equal to B, the result is a boolean false.

In the case of test for greater than or equal ‘>=’, if A is greater than or equal to B, the result is a boolean true. If A is less than B, the result is a boolean false. Let us use an ‘if-else’ statement to better understand the application.

The <instance_A>, <instance_B> are data instances of any data type. In the first process, the test for greater than if <instance_A> is greater then and not equal to <instance_B> only then the <instance_C> is given a binary 1 value. If <instance_A> less than or equal to <instance_B> only then the <instance_C> is given a binary 0 value.

In the second process, the test for greater than or equal if <instance_A> is greater than or equal to <instance_B> only then the <instance_C> is given a binary 1 value. If <instance_A> less <instance_B> only then the <instance_C> is given a binary 0 value.

Logical operators perform logic operations between logical array or boolean data. Logical operators in VHDL include:

  • Logical AND  and
  • Logical OR  or
  • Logical NOT of AND  nand
  • Logical NOT of OR  nor
  • Logical Exclusive of OR  xor
  • Logical Exclusive of NOT of OR  xnor

Logical AND

Performs logical AND operation with a logical array or boolean.

The and keyword is used to specify an AND between the two elements. The AND operation is performed and stored in their respective <logical_array_storage>  or  <boolean_storage>. You can check out the truth table of the AND operation here .

Performs logical OR operation with a logical array or boolean.

The or keyword is used to specify an OR between the two elements. The OR operation is performed and stored in their respective <logical_array_storage>  or  <boolean_storage>. You can check out the truth table of the OR operation here .

Logical NAND

Performs logical NAND operation with a logical array or boolean.

The nand keyword is used to specify a NAND between the two elements. The nand operation is performed and stored in their respective <logical_array_storage>  or  <boolean_storage>. You can check out the truth table of the NAND operation here.

Logical NOR

Performs logical NOR operation with a logical array or boolean.

The nor keyword is used to specify a NOR between the two elements. The NOR operation is performed and stored in their respective <logical_array_storage>  or  <boolean_storage>. You can check out the truth table of the NOR operation here .

Logical XOR

Performs logical XOR operation with a logical array or boolean.

The xor keyword is used to specify an XOR between the two elements. The XOR operation is performed and stored in their respective <logical_array_storage>  or  <boolean_storage>. You can check out the truth table of the XOR operation here.

Logical XNOR

The xnor keyword is used to specify an XNOR between the two elements. The XNOR operation is performed and stored in their respective <logical_array_storage>  or  <boolean_storage>. You can check out the truth table of the XNOR operation here .

As you can see, operators in VHDL (or any language for that matter) are easy to use and also very powerful tools. With an increase in the scale of our designs, smart implementation of these operators can help us make our program efficient and save on resources.

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vhdl Getting started with vhdl Signals vs. variables, a brief overview of the simulation semantics of VHDL

This example deals with one of the most fundamental aspects of the VHDL language: the simulation semantics. It is intended for VHDL beginners and presents a simplified view where many details have been omitted (postponed processes, VHDL Procedural Interface, shared variables...) Readers interested in the real complete semantics shall refer to the Language Reference Manual (LRM).

Signals and variables

Most classical imperative programming languages use variables. They are value containers. An assignment operator is used to store a value in a variable:

and the value currently stored in a variable can be read and used in other statements:

VHDL also uses variables and they have exactly the same role as in most imperative languages. But VHDL also offers another kind of value container: the signal. Signals also store values, can also be assigned and read. The type of values that can be stored in signals is (almost) the same as in variables.

So, why having two kinds of value containers? The answer to this question is essential and at the heart of the language. Understanding the difference between variables and signals is the very first thing to do before trying to program anything in VHDL.

Let us illustrate this difference on a concrete example: the swapping.

Note: all the following code snippets are parts of processes. We will see later what processes are.

swaps variables a and b . After executing these 3 instructions, the new content of a is the old content of b and conversely. Like in most programming languages, a third temporary variable ( tmp ) is needed. If, instead of variables, we wanted to swap signals, we would write:

with the same result and without the need of a third temporary signal!

Note: the VHDL signal assignment operator <= is different from the variable assignment operator := .

Let us look at a second example in which we assume that the print subprogram prints the decimal representation of its parameter. If a is an integer variable and its current value is 15, executing:

will print:

If we execute this step by step in a debugger we can see the value of a changing from the initial 15 to 30, 25 and finally 5.

But if s is an integer signal and its current value is 15, executing:

If we execute this step by step in a debugger we will not see any value change of s until after the wait instruction. Moreover, the final value of s will not be 15, 30, 25 or 5 but 3!

This apparently strange behavior is due the fundamentally parallel nature of digital hardware, as we will see in the following sections.

Parallelism

VHDL being a Hardware Description Language (HDL), it is parallel by nature. A VHDL program is a collection of sequential programs that run in parallel. These sequential programs are called processes:

The processes, just like the hardware they are modelling, never end: they are infinite loops. After executing the last instruction, the execution continues with the first.

As with any programming language that supports one form or another of parallelism, a scheduler is responsible for deciding which process to execute (and when) during a VHDL simulation. Moreover, the language offers specific constructs for inter-process communication and synchronization.

The scheduler maintains a list of all processes and, for each of them, records its current state which can be running , run-able or suspended . There is at most one process in running state: the one that is currently executed. As long as the currently running process does not execute a wait instruction, it continues running and prevents any other process from being executed. The VHDL scheduler is not preemptive: it is each process responsibility to suspend itself and let other processes run. This is one of the problems that VHDL beginners frequently encounter: the free running process.

Note: variable a is declared locally while signals s and r are declared elsewhere, at a higher level. VHDL variables are local to the process that declares them and cannot be seen by other processes. Another process could also declare a variable named a , it would not be the same variable as the one of process P3 .

As soon as the scheduler will resume the P3 process, the simulation will get stuck, the simulation current time will not progress anymore and the only way to stop this will be to kill or interrupt the simulation. The reason is that P3 has not wait statement and will thus stay in running state forever, looping over its 3 instructions. No other process will ever be given a chance to run, even if it is run-able .

Even processes containing a wait statement can cause the same problem:

Note: the VHDL equality operator is = .

If process P4 is resumed while the value of signal s is 3, it will run forever because the a = 16 condition will never be true.

Let us assume that our VHDL program does not contain such pathological processes. When the running process executes a wait instruction, it is immediately suspended and the scheduler puts it in the suspended state. The wait instruction also carries the condition for the process to become run-able again. Example:

means suspend me until the value of signal s changes . This condition is recorded by the scheduler. The scheduler then selects another process among the run-able , puts it in running state and executes it. And the same repeats until all run-able processes have been executed and suspended.

Important note: when several processes are run-able , the VHDL standard does not specify how the scheduler shall select which one to run. A consequence is that, depending on the simulator, the simulator's version, the operating system, or anything else, two simulations of the same VHDL model could, at one point, make different choices and select a different process to execute. If this choice had an impact on the simulation results, we could say that VHDL is non-deterministic. As non-determinism is usually undesirable, it would be the responsibility of the programmers to avoid non-deterministic situations. Fortunately, VHDL takes care of this and this is where signals enter the picture.

Signals and inter-process communication

VHDL avoids non determinism using two specific characteristics:

  • Processes can exchange information only through signals
Note: VHDL comments extend from -- to the end of the line.
  • The value of a VHDL signal does not change during the execution of processes

Every time a signal is assigned, the assigned value is recorded by the scheduler but the current value of the signal remains unchanged. This is another major difference with variables that take their new value immediately after being assigned.

Let us look at an execution of process P5 above and assume that a=5 , s=1 and r=0 when it is resumed by the scheduler. After executing instruction a := s + 1; , the value of variable a changes and becomes 2 (1+1). When executing the next instruction r <= a; it is the new value of a (2) that is assigned to r . But r being a signal, the current value of r is still 0. So, when executing a := r + 1; , variable a takes (immediately) value 1 (0+1), not 3 (2+1) as the intuition would say.

When will signal r really take its new value? When the scheduler will have executed all run-able processes and they will all be suspended. This is also referred to as: after one delta cycle . It is only then that the scheduler will look at all the values that have been assigned to signals and actually update the values of the signals. A VHDL simulation is an alternation of execution phases and signal update phases. During execution phases, the value of the signals is frozen. Symbolically, we say that between an execution phase and the following signal update phase a delta of time elapsed. This is not real time. A delta cycle has no physical duration.

Thanks to this delayed signal update mechanism, VHDL is deterministic. Processes can communicate only with signals and signals do not change during the execution of the processes. So, the order of execution of the processes does not matter: their external environment (the signals) does not change during the execution. Let us show this on the previous example with processes P5 and P6 , where the initial state is P5.a=5 , P6.a=10 , s=17 , r=0 and where the scheduler decides to run P5 first and P6 next. The following table shows the value of the two variables, the current and next values of the signals after executing each instruction of each process:

With the same initial conditions, if the scheduler decides to run P6 first and P5 next:

As we can see, after the execution of our two processes, the result is the same whatever the order of execution.

This counter-intuitive signal assignment semantics is the reason of a second type of problems that VHDL beginners frequently encounter: the assignment that apparently does not work because it is delayed by one delta cycle. When running process P5 step-by-step in a debugger, after r has been assigned 18 and a has been assigned r + 1 , one could expect that the value of a is 19 but the debugger obstinately says that r=0 and a=1 ...

Note: the same signal can be assigned several times during the same execution phase. In this case, it is the last assignment that decides the next value of the signal. The other assignments have no effect at all, just like if they never had been executed.

It is time to check our understanding: please go back to our very first swapping example and try to understand why:

actually swaps signals r and s without the need of a third temporary signal and why:

would be strictly equivalent. Try to understand also why, if s is an integer signal and its current value is 15, and we execute:

the two first assignments of signal s have no effect, why s is finally assigned 3 and why the two printed values are 15 and 3.

Physical time

In order to model hardware it is very useful to be able to model the physical time taken by some operation. Here is an example of how this can be done in VHDL. The example models a synchronous counter and it is a full, self-contained, VHDL code that could be compiled and simulated:

In process P1 the wait instruction is not used to wait until the value of a signal changes, like we saw up to now, but to wait for a given duration. This process models a clock generator. Signal clk is the clock of our system, it is periodic with period 20 ns (50 MHz) and has duty cycle.

Process P2 models a register that, if a rising edge of clk just occurred, assigns the value of its input nc to its output c and then waits for the next value change of clk .

Process P3 models an incrementer that assigns the value of its input c , incremented by one, to its output nc ... with a physical delay of 5 ns. It then waits until the value of its input c changes. This is also new. Up to now we always assigned signals with:

which, for the reasons explained in the previous sections, we can implicitly translate into:

This small digital hardware system could be represented by the following figure:

A synchronous counter

With the introduction of the physical time, and knowing that we also have a symbolic time measured in delta , we now have a two dimensional time that we will denote T+D where T is a physical time measured in nano-seconds and D a number of deltas (with no physical duration).

The complete picture

There is one important aspect of the VHDL simulation that we did not discuss yet: after an execution phase all processes are in suspended state. We informally stated that the scheduler then updates the values of the signals that have been assigned. But, in our example of a synchronous counter, shall it update signals clk , c and nc at the same time? What about the physical delays? And what happens next with all processes in suspended state and none in run-able state?

The complete (but simplified) simulation algorithm is the following:

  • Set current time Tc to 0+0 (0 ns, 0 delta-cycle)
  • Initialize all signals.
  • Record the values and delays of signal assignments.
  • Record the conditions for the process to resume (delay or signal change).
  • The resume time of processes suspended by a wait for <delay> .
  • The next time at which a signal value shall change.
  • Update signals that need to be.
  • Put in run-able state all processes that were waiting for a value change of one of the signals that has been updated.
  • Put in run-able state all processes that were suspended by a wait for <delay> statement and for which the resume time is Tc .
  • If Tn is infinity, stop simulation. Else, start a new simulation cycle.

Manual simulation

To conclude, let us now manually exercise the simplified simulation algorithm on the synchronous counter presented above. We arbitrary decide that, when several processes are run-able, the order will be P3 > P2 > P1 . The following tables represent the evolution of the state of the system during the initialization and the first simulation cycles. Each signal has its own column in which the current value is indicated. When a signal assignment is executed, the scheduled value is appended to the current value, e.g. a/b@T+D if the current value is a and the next value will be b at time T+D (physical time plus delta cycles). The 3 last columns indicate the condition to resume the suspended processes (name of signals that must change or time at which the process shall resume).

Initialization phase:

Simulation cycle #1.

Note: during the first simulation cycle there is no execution phase because none of our 3 processes has its resume condition satisfied. P2 is waiting for a value change of clk and there has been a transaction on clk , but as the old and new values are the same, this is not a value change .

Simulation cycle #2

Note: again, there is no execution phase. nc changed but no process is waiting on nc .

Simulation cycle #3

Simulation cycle #4, simulation cycle #5.

Note: one could think that the nc update would be scheduled at 15+2 , while we scheduled it at 15+0 . When adding a non-zero physical delay (here 5 ns ) to a current time ( 10+2 ), the delta cycles vanish. Indeed, delta cycles are useful only to distinguish different simulation times T+0 , T+1 ... with the same physical time T . As soon as the physical time changes, the delta cycles can be reset.

Simulation cycle #6

Simulation cycle #7, simulation cycle #8, simulation cycle #9, simulation cycle #10, simulation cycle #11, got any vhdl question.

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Signal Assignments in VHDL: with/select, when/else and case

Sometimes, there is more than one way to do something in VHDL. OK, most of the time , you can do things in many ways in VHDL. Let’s look at the situation where you want to assign different values to a signal, based on the value of another signal.

With / Select

The most specific way to do this is with as selected signal assignment. Based on several possible values of a , you assign a value to b . No redundancy in the code here. The official name for this VHDL with/select assignment is the selected signal assignment .

When / Else Assignment

The construct of a conditional signal assignment is a little more general. For each option, you have to give a condition. This means that you could write any boolean expression as a condition, which give you more freedom than equality checking. While this construct would give you more freedom, there is a bit more redundancy too. We had to write the equality check ( a = ) on every line. If you use a signal with a long name, this will make your code bulkier. Also, the separator that’s used in the selected signal assignment was a comma. In the conditional signal assignment, you need the else keyword. More code for the same functionality. Official name for this VHDL when/else assignment is the conditional signal assignment

Combinational Process with Case Statement

The most generally usable construct is a process. Inside this process, you can write a case statement, or a cascade of if statements. There is even more redundancy here. You the skeleton code for a process (begin, end) and the sensitivity list. That’s not a big effort, but while I was drafting this, I had put b in the sensitivity list instead of a . Easy to make a small misstake. You also need to specify what happens in the other cases. Of course, you could do the same thing with a bunch of IF-statements, either consecutive or nested, but a case statement looks so much nicer.

While this last code snippet is the largest and perhaps most error-prone, it is probably also the most common. It uses two familiar and often-used constructs: the process and the case statements.

Designing Circuits with VHDL

1. introduction, 2. combinational circuits, signal assignments in vhdl.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fullAdder is     port(  A,B: in  std_logic;  -- input bits for this stage            Ci:   in  std_logic; -- carry into this stage            S:    out std_logic; -- sum bit            Co:   out std_logic  -- carry out of this stage     ); end fullAdder; architecture a1 of fullAdder is begin     S <= A xor B xor Ci;     Co <= (A and B) or ((A xor B) and Ci); end a1;

Processes and Conditional Statements

if a = '0' then     x <= a;     y <= b; elsif a = b then     x <= '0';   y <= '1'; else     x <= not b; y <= not b; end if;
Every signal that is assigned a value inside a process must be defined for all possible conditions.

Case Statements

Structural vhdl, 3. sequential circuits.

assignment operators vhdl

busy   is high when the circuit is in the middle of performing an operation;             while busy is high, the insert and delete inputs are ignored; the             outputs are not required to have the correct values when busy is high empty     is high when there are no pairs stored in the priority queue; delete             operations are ignored in this case full      is high when there is no room for any additional pairs to be stored;             insert operations are ignored in this case
  • For adjacent pairs in the bottom row, the pair to the left has a key that is less than or equal to that of the pair on the right.
  • For pairs that are in the same column, the key of the pair in the bottom row is less than or equal to that of the pair in the top row.
  • In both rows, the empty blocks (those with dp =0) are to the right and either both rows have the same number of empty blocks or the top row has one more than the bottom row.
entity priQueue is     Port (clk, reset : in std_logic;           insert, delete : in std_logic;           key, value : in std_logic_vector(wordSize-1 downto 0);           smallValue : out std_logic_vector(wordSize-1 downto 0);           busy, empty, full : out std_logic     );    end priQueue; architecture a1 of priQueue is constant rowSize: integer := 4; -- local constant declaration type pqElement is record     dp: std_logic;     key: std_logic_vector(wordSize-1 downto 0);     value: std_logic_vector(wordSize-1 downto 0); end record pqElement; type rowTyp is array(0 to rowSize-1) of pqElement; signal top, bot: rowTyp; type state_type is (ready, inserting, deleting); signal state: state_type; begin     process(clk) begin         if rising_edge(clk) then             if reset = '1' then                 for i in 0 to rowSize-1 loop                     top(i).dp <= '0'; bot(i).dp <= '0';                 end loop;                 state <= ready;             elsif state = ready and insert = '1' then                 if top(rowSize-1).dp /= '1' then                     for i in 1 to rowSize-1 loop                         top(i) <= top(i-1);                     end loop;                     top(0) <= ('1',key,value);                     state <= inserting;                 end if;             elsif state = ready and delete = '1' then                 if bot(0).dp /= '0' then                     for i in 0 to rowSize-2 loop                         bot(i) <= bot(i+1);                     end loop;                     bot(rowSize-1).dp <= '0';                     state <= deleting;                 end if;             elsif state = inserting or state = deleting then                 for i in 0 to rowSize-1 loop                     if top(i).dp = '1' and                         (top(i).key < bot(i).key                          or bot(i).dp = '0') then                         bot(i) <= top(i); top(i) <= bot(i);                     end if;                end loop;                 state <= ready;             end if;         end if;     end process;     smallValue <= bot(0).value when bot(0).dp = '1' else                   (others => '0');     empty <= not bot(0).dp;     full <= top(rowSize-1).dp;     busy <= '1' when state /= ready else '0'; end a1;

4. Functions and Procedures

package commonConstants is     constant lgWordSize: integer := 4;        constant wordSize: integer := 2**lgWordSize; end package commonConstants; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.commonConstants.all; entity firstOne is     Port (a: in std_logic_vector(0 to wordSize-1);           x: out std_logic_vector (lgWordSize downto 0)      ); end firstOne; architecture a1 of firstOne is procedure encode(x: in std_logic_vector(0 to wordSize-1);                 indx: out std_logic_vector(lgWordSize-1 downto 0);                 errFlag: out std_logic) is -- Unary to binary encoder. -- Input x is assumed to have at most a single 1 bit. -- Indx is equal to the index of the bit that is set. -- If no bits are set, errFlag bit is made high. -- This is conceptually simple. -- --        indx(0) is OR of x(1),x(3),x(5), ... --        indx(1) is OR of x(2),x(3), x(6),x(7), x(10),x(11), ... --        indx(2) is OR of x(4),x(5),x(6),x(7), x(12),x(13),x(14(,x(15),... -- -- but it's tricky to code so it works for different word sizes. type vec is array(0 to lgWordSize-1) of std_logic_vector(0 to (wordSize/2)-1); variable fOne: vec; variable anyOne: std_logic_vector(0 to wordSize-1); begin     -- fOne(0)(j) is OR of first j bits in x1,x3,x5,...     -- fOne(1)(j) is OR of first j bits in x2,x3, x6,x7, x10,x11,...     -- fOne(2)(j) is OR of first j bits in x4,x5,x6,x7, x12,x13,x14,x15,...     for i in 0 to lgWordSize-1 loop         for j in 0 to (wordSize/(2**(i+1)))-1 loop                        for h in 0 to (2**i)-1 loop                 if j = 0 and h = 0 then                     fOne(i)(0) := x(2**i);                 else                     fOne(i)((2**i)*j+h) := fOne(i)((2**i)*j+h-1) or                                            x(((2**i)*(2*j+1))+h);                 end if;             end loop;         end loop;         indx(i) := fOne(i)((wordSize/2)-1);     end loop;     anyOne(0) := x(0);     for i in 1 to wordSize-1 loop         anyOne(i) := anyOne(i-1) or x(i);     end loop;     errFlag := not anyOne(wordSize-1); end procedure encode; function firstOne(x: std_logic_vector(0 to wordSize-1))                         return std_logic_vector is -- Returns the index of the first 1 in bit string x. -- If there are no 1's in x, the value returned has a -- 1 in the high order bit. variable allZero: std_logic_vector(0 to wordSize-1); variable fOne: std_logic_vector(0 to wordSize-1); variable rslt: std_logic_vector(lgWordSize downto 0); begin     allZero(0) := not x(0);     fOne(0) := x(0);     for i in 1 to wordSize-1 loop         allZero(i) := (not x(i)) and allZero(i-1);         fOne(i) := x(i) and allZero(i-1);     end loop;     encode(fOne,rslt(lgWordSize-1 downto 0),rslt(lgWordSize));     return rslt; end function firstOne; begin     x <= firstOne(a); end a1;

5. Closing Remarks

VHDL has several types of pre-defined operators that are,

  • Shift operators
  • Arithmetic operators
  • Assignment operators
  • Logical operators
  • Relational operators
  • Concatenation operators

Shift operators :

  • Shift operators are used for shifting data.
  • The syntax is as follows,

<left operand>

<shift operation>

<right operand>.

  • The left should have type BIT_VECTOR, whereas the right operand should have INTEGER.
  • The shift operators are :

sll Shift left logic

srl Shift right logic

Arithmetic operators :

In arithmetic operators the data is of type INTEGER,SIGNED, UNSIGNED, or REAL. Further, if the std_logic_signed or the std_logic_unsigned package of the ieee library required to be used.

The arithmetic operators are :

  • - Subtraction
  • * Multiplication
  • ** Exponentiation
  • MOD Modulus
  • REM Remainder
  • ABS Absolute value

Assignment operators :

The assignment operators are used to assign values to signals, variables, and constants. The assignment operators are,

<= Used to assign a value to a SIGNAL.

:= Used to assign a value to a VARIABLE, CONSTANT, or GENERIC.

=> Used to assign values to OTHERS.

Logical operators :

The logical operators are used to perform logical operations. The data should of type type BIT, STD_LOGIC, or STD_ULOGIC.

The logical operators are,

Comparison operators :

Comparison operators are used for making comparisons. The data can be of any type. The comparison operators are,

  • /= Not equal to
  • < Less than
  • > Greater than
  • <= Less than or equal to
  • >= Greater than or equal to

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Book cover

Introduction to Logic Circuits & Logic Design with VHDL pp 285–327 Cite as

VHDL (Part 2)

  • Brock J. LaMeres 2  
  • First Online: 20 March 2019

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In Chap. 5 VHDL was presented as a way to describe the behavior of concurrent systems. The modeling techniques presented were appropriate for combinational logic because these types of circuits have outputs dependent only on the current values of their inputs. This means a model that continuously performs signal assignments provides an accurate model of this circuit behavior. In Chap. 7 sequential logic storage devices were presented that did not continuously update their outputs based on the instantaneous values of their inputs. Instead, sequential storage devices only update their outputs based upon an event, most often the edge of a clock signal. The modeling techniques presented in Chap. 5 are unable to accurately describe this type of behavior. In this chapter we describe the VHDL constructs to model signal assignments that are triggered by an event in order to accurately model sequential logic. We can then use these techniques to describe more complex sequential logic circuits such as finite state machines and register transfer level systems. This chapter will also present how to create test benches and look at commonly used packages that increase the capability and accuracy with which VHDL can model modern systems. The goal of this chapter is to give an understanding of the full capability of hardware description languages.

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LaMeres, B.J. (2019). VHDL (Part 2). In: Introduction to Logic Circuits & Logic Design with VHDL . Springer, Cham. https://doi.org/10.1007/978-3-030-12489-2_8

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COMMENTS

  1. VHDL Logical Operators and Signal Assignments for Combinational Logic

    The first of these is the VHDL assignment operator (<=) which must be used for all signals. This is roughly equivalent to the = operator in most other programming languages. In addition to signals, we can also define variables which we use inside of processes. In this case, we would have to use a different assignment operator (:=).

  2. syntax

    Contrary to the book Digital Mclogic Design by Bryan Mealy VHDL has no assignment operators. Assignment is a basic operation found in assignment statements and object and interface declarations. - user16145658 Feb 15, 2023 at 22:18 Add a comment 4 Answers Sorted by: 10 Well, <= is assignment. signal <= A or B;

  3. Assignment Symbol

    VHDL assignments are used to assign values from one object to another. In VHDL there are two assignment symbols: <= Assignment of Signals := Assignment of Variables and Signal Initialization Either of these assignment statements can be said out loud as the word "gets".

  4. PDF VHDL Syntax Reference

    1. Bits, Vectors, Signals, Operators, Types 1.1 Bits and Vectors in Port Bits and vectors declared in port with direction. Example: port ( a : in std_logic; -- signal comes in to port a from outside : out std_logic; -- signal is sent out to the port b : inout std_logic; -- bidirectional port

  5. What' s the difference between <= and := in VHDL

    You use := to do variable assignment, which takes place immediately. So if you have a signal, you always use <=. If you have a variable, you always use :=. Some places where this is not quite that case that you will commonly run into, for instance, initialization, where := is used even for signals. So:

  6. Operators in VHDL

    The operators in VHDL are divided into four categories: Arithmetic operators Shift operators Relational operators Logical operators Each operator serves a well-defined purpose, and here we will learn to use these operators to our advantage in our programs. We'll be using all of these operators extensively in our future modules in this VHDL course.

  7. VHDL Reference Guide

    Assignments may be made from signals to variables and vice-versa, providing the types match: process (A, B, C, SEL) variable X : integer range 0 to 7; begin if SEL = '1' then X := B; else X := C; end if; Z <= A + X; end process;

  8. VHDL Reference Guide

    A conditional signal assignment will usually result in combinational logic being generated. Assignment to 'Z' will normally generate tri-state drivers. ... In VHDL-93, any signal assigment statement may have an optinal label. VHDL-93 defines an unaffected keyword, which indicates a condition when a signal is not given a new assignment:

  9. Modeling Concurrent Functionality in VHDL

    3.1.1 Assignment Operator. VHDL uses <= for all signal assignments and := for all variable and initialization assignments. These assignment operators work on all data types. The target of the assignment goes on the left of these operators, and the input arguments go on the right. Example:

  10. vhdl Tutorial => Signals vs. variables, a brief overview of the

    Note: the VHDL signal assignment operator <= is different from the variable assignment operator :=. Let us look at a second example in which we assume that the print subprogram prints the decimal representation of its parameter. If a is an integer variable and its current value is 15, executing:

  11. PDF VHDL Operator Operation

    Useful to enter constants. work in a similar way to produce signed and unsigned values. Produces a standard logic vector of "0111". Converts a standard logic vector to an integer. Useful for array indexing when using a std_logic_vector signal for the array index. Produces an integer value of 7.

  12. Designing Digital Circuits Using VHDL©

    Here, A, B, C and D are names of VHDL signals; <= is the signal assignment operator and the keywords and, or and not are the familiar logical operators. The parentheses are used to determine the order of operations (in this case, they are not strictly necessary, but do help make the meaning more clear) and the semicolon terminates the assignment.

  13. Signal Assignments in VHDL: with/select, when/else and case

    Signal Assignments in VHDL: with/select, when/else and case Posted on 2011-07-04 by Philippe Faes Tagged as: VHDL syntax Sometimes, there is more than one way to do something in VHDL. OK, most of the time, you can do things in many ways in VHDL.

  14. VHDL (Part 1)

    5.5.1 VHDL Operators. There are a variety of pre-defined operators in the IEEE standard package. It is important to note that operators are defined to work on specific data types and that not all operators are synthesizable. 5.5.1.1 Assignment Operator. VHDL uses <= for all signal assignments and: = for all variable and initialization ...

  15. VHDL Basics

    1. VHDL Basics 2. Objectives 3. Course Outline 4. VHDL Basics 5. VHDL Design Units 6. Architeture Modeling Fundamentals 7. Logic Synthesis 8. Designing Hierarchically 9.

  16. VHDL Reference Guide

    The logical operators are predefined for bit, boolean, bit_vector, linear arrays of boolean, std_logic and std_logic_vector types. They return a value of the same type: ... xnor has been added to the logical operators in VHDL-94. New shift and rotate operators are defined for one-dimensional arrays of bit or boolean:

  17. Designing Circuits with VHDL

    VHDL allows us to specify circuits with equations in much the same way. A <= (B and C) or (not D); Here, A, B, C and D are names of VHDL signals; <= is the concurrent signal assignment operator and the keywords and, or and not are the familiar logical operators. The parentheses are used to determine the order of operations (in this case, they ...

  18. VHDL Online Help

    A variable assignment statement replaces the current value of a variable with a new value specified by an expression. Simplified Syntax variable_name := expression ; Description The variable assignment statement modifies the value of the variable. The new value of the variable is obtained by assigning an expression to this variable.

  19. VHDL || Electronics Tutorial

    Operators. VHDL has several types of pre-defined operators that are, Shift operators; Arithmetic operators; Assignment operators; Logical operators; Relational operators; Concatenation operators; Shift operators : Shift operators are used for shifting data. The syntax is as follows, <left operand> <shift operation> <right operand>.

  20. concurrent and conditional signal assignment (VHDL)

    In VHDL, there are two types for signal assignment: concurrent ----> when...else ----> select...when...else sequential ----> if...else ----> case...when Problem is that some say that when...else conditions are checked line by line (king of sequential) while select...when...else conditionals are checked once. See this reference for example.

  21. Concurrent Conditional and Selected Signal Assignment in VHDL

    The selected signal assignment allows us to implement the functionality of a multiplexer. For example, the VHDL code describing the multiplexer of Figure 3 will be. with control_expression select output_signal <= value_1 when option_1, value_2 when option_2, ... value_n when option_n; Here, the value of the control_expression will be compared ...

  22. VHDL (Part 2)

    What is the assignment operator for variables? Section 8.2: Conditional Programming Constructs. 8.2.1. Design a VHDL model to implement the behavior described by the 4-input truth table in Fig. 8.4. Use a process and an if/then statement. Use std_logic and std_logic_vector types for your signals. Declare the entity to match the block diagram ...